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Abstract

A method for forming multiple layer metallurgy, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion, that is the positive charge between the first via layer and the SOG is described. A semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within semiconductor substrate electrically separating certain of these source/drain regions from one another are provided. A passivation layer is formed over the surfaces of said patterns. Then the multilayer metallurgy is formed thereover by opening a pattern of openings through the passivation layer to at least some of the source/drain regions, depositing and patterning a first metallurgy layer in contact with the pattern of openings, forming a first via dielectric layer over the pattern of first metallurgy layer, exposing the first silicon oxide via dielectric layer to a nitrogen plasma, forming a spin-on-glass layer over the via dielectric layer and curing the layer, forming a second via dielectric layer over the spin-on-glass layer, forming a pattern of openings in the second via layer, the spin-on-glass layer, and the first via layer, and depositing and patterning a second metallurgy layer through the openings to make electrical contact with the first metallurgy layer.

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