Wire interconnect structures for connecting an integrated circuit to a substrate

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United States of America Patent

PATENT NO 5334804
SERIAL NO

07977571

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the 'outside world,' such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprises an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one anther so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.

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Patent Owner(s)

Patent OwnerAddress
FUJITSU LIMITEDKAWASAKI

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Beilin, Solomon I San Carlos, CA 53 3669
Chou, William T Cupertino, CA 29 1273
Horine, David A Los Altos, CA 23 905
Love, David G Pleasanton, CA 17 847
Moresco, Larry L San Carlos, CA 23 1137
Wong, Connie M Fremont, CA 4 322

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