Importance

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Abstract

A semiconductor memory cell (10) including cross coupled CMOS transistors (12, 14) wherein an N-channel transistor (20) overlies a central portion of each of a first and second active regions (13, 13') at a position intermediate to two word lines (40, 42) which overlie end portions of the active regions (13, 13'). P-channel pull-up transistors (18, 22) overlie the N-channel transistors (16, 20) and share common intermediate gate electrodes (27, 29). Staggered bit line contacts (48, 50) are formed to each active region (13, 13') adjacent to each word line (40, 42) and opposite to the N-type transistors (16, 20). Staggered Vss contacts (52, 54) are provided to each active region (13, 13') adjacent to the word lines (40, 42) and opposite to the bit line contacts (48, 50). A Vss signal is electrically coupled to the N-channel transistors (16, 20) by a doped region (21) formed in the first and second active regions (13, 13' ) which cross under the word lines (40, 42). A Vss contact land (71) is provided by a conductive body overlying the active region in the staggered Vss contacts (52, 54) and a portion of the adjacent word lines (40, 42) and at least a portion of the CMOS transistors (12, 14) opposite the word lines (40, 42).

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First Claim