Fast settling phase locked loop
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United States of America Patent
Stats
-
Aug 2, 1994
Grant Date -
N/A
app pub date -
Mar 29, 1993
filing date -
Mar 29, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A phase locked loop including a switch between a phase detector output and a VCO input to open the PLL during a frequency change is provided. While the PLL is open, an analog error correction signal is generated by sampling any residual error coming from the phase detector, and generating the analog error correction signal to counter the residual error. Once analog error correction signal is available, the switch is closed and the error correction signal is added to the phase detector output and the PLL is allowed to settle to an optimized frequency.
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