Configuration features in a configurable logic array

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United States of America Patent

PATENT NO 5336950
SERIAL NO

08015415

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Abstract

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The present invention is directed to various configuration features of a logic array that includes a plurality of individually configurable logic cells arranged in a matrix. These features include reconfiguration logic for reconfiguring logic cells in a selected portion of the matrix using a window-based protocol. The array also includes configuration data storage means for storing configuration data utilizable for configuring the logic elements, wherein each logic element includes a working data storage register, and reset circuitry for modifying the configuration data without modifying the working data. The array further includes read disable circuitry and write disable circuitry for disabling read access and write access, respectively, to the configuration data. The array further includes a comparison protocol mechanism for checking the configuration data against data on the array pins. The array further includes a configuration circuit for generating external addresses and that can be controlled through a data configuration file fetched from an external storage medium.

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Patent Owner(s)

  • NATIONAL SEMICONDUCTOR CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Camarota, Rafael C San Jose, CA 51 1566
Hawley, David Belmont, CA 21 661
Moni, Shankar Santa Clara, CA 26 638
Pickett, Scott Los Gatos, CA 5 380
Popli, Sanjay Sunnyvale, CA 4 501

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