Semiconductor memory device having an insulating film and a trap film joined in a channel region
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United States of America Patent
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Aug 16, 1994
Grant Date -
N/A
app pub date -
Feb 3, 1993
filing date -
Oct 31, 1991
priority date (Note) -
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Abstract
A semiconductor memory device and a method for producing the same are provided, wherein memory cells, in each of which a MONOS- or MNOS-type memory transistor is combined with an enhancement transistor in a reduced cell area, are arranged in a matrix configuration. With such a device and a method, an extremely high integration of memory cells can be realized with a reduced production cost. The semiconductor memory device of the present invention includes a gate insulating film and a trap film which are joinedly formed on a channel region of a semiconductor substrate of a first conductive type. A gate electrode extends over the two films. Source/drain regions are formed on opposite sides of the gate electrode
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