Importance

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Abstract

Three delay lines may have common characteristics. The first delay line delays the rising edge of an input signal and a first inverter inverts this signal to provide a falling edge. A second inverter inverts the rising edge of the input signal to produce a falling edge which is introduced to the second delay line in a second path with the second inverter. The signals from the two paths may be introduced to a comparator which produces a control signal having logic levels dependent upon the relative times that the falling edges occur for the signals in the two paths. For example, the control signal may have the first logic level when the falling edge occurs first in the first path and the control signal may have the second logic level when the falling edge occurs first in the second path. The voltage from a charge pump is adjusted in accordance with the logic level of the control signal. This voltage is introduced to the first and second delay lines to adjust their delay to minimize the time difference in the falling edges of the signals from these lines. This voltage is also introduced to the third delay line to adjust its delay in accordance with the adjustments in the delays in the first and second lines. In this way, the third delay line provides the same time for rising edges and falling edges in data signals introduced to the line.

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First Claim