Importance

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Abstract

A synchronous dynamic random-access memory has transparent latch circuits that latch address signals in synchronization with a clock signal. An X-address is latched following activation of a first control signal; a Y-address is latched following activation of a second control signal. Data selected by the latched X- and Y-addresses are held in a data latch and output through a tri-state output circuit in synchronization with the clock signal. Data output starts a certain number of clock cycles from activation of the first control signal. The data can be output for one clock cycle, the same data can be output for two or more consecutive clock cycles, or different data can be output in consecutive clock cycles in an order determined by certain bits in the X- and Y-addresses.

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First Claim