Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
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United States of America Patent
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Aug 23, 1994
Grant Date -
N/A
app pub date -
Jul 17, 1992
filing date -
Jul 17, 1992
priority date (Note) -
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Abstract
Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more 'efficiently' than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.
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