Flexible configuration logic array block for programmable logic devices
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United States of America Patent
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Aug 23, 1994
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N/A
app pub date -
Apr 19, 1993
filing date -
Apr 19, 1993
priority date (Note) -
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Abstract
A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.
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