Testability architecture and techniques for programmable interconnect architecture
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United States of America Patent
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Aug 23, 1994
Issued Date -
N/A
app pub date -
Oct 7, 1992
filing date -
Sep 19, 1986
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Abstract
In an integrated circuit including a first conductor disposed in a first direction, a plurality of second conductors forming intersections with the first conductor, and a plurality of antifuses connected between the first conductor and the second conductors at the intersections, a method for testing the integrity of the plurality of antifuses after attempting to program a selected one of the antifuses, including the steps of precharging each of the second conductors to a first preselected voltage potential such that a selected dynamic voltage is placed on each of the second conductors; placing a second voltage potential on the first conductor, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of a good antifuse; waiting a preselected time; and sensing the voltage potential on each of the second conductors.
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