Dynamic random access memory device having addressing section and/or data transferring path arranged in pipeline architecture
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United States of America Patent
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Aug 23, 1994
Grant Date -
N/A
app pub date -
Mar 23, 1993
filing date -
Mar 26, 1992
priority date (Note) -
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Abstract
A dynamic random access memory device is responsive to a row address signal and a column address signal supplied in synchronism with a system clock signal for providing a data path from a data input/output port and a memory cell selected from the memory cell array, and latch circuits are provided in the addressing section and the data transferring path for temporarily storing address decoded signal and write-in and read-out data bits in response to latch control signals higher in frequency than the system clock signal, thereby controlling the data stream in a pipeline fashion.
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