Importance

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Abstract

A method for rapidly transferring serial data in a two conductor busing arrangement in which one conductor is utilized to transfer data and the other conductor is utilized to transfer clock signals, and in which a plurality of components are connected to the two conductors, at least one of which is capable of acting as a bus master including the steps of providing clock signals on the clock conductor which are active on both edges, placing a special signal on the data conductor to indicate the start of an operation, placing address data on the data conductor to indicate an address on the data conductor, placing data on the data conductor to indicate the type of transfer to be made, acknowledging the receipt of the address by a component being addressed, transferring data on the data conductor, placing a special signal on the data conductor to indicate the end of the data transfer, transferring a signal indicating a parity count, and placing another special signal on the data conductor to indicate the end of the operation.

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First Claim