US Patent No: 5,342,807

Number of patents in Portfolio can not be more than 2000

Soft bond for semiconductor dies

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Importance

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Abstract

On a semiconductor integrated circuit die, a semipermanent electrical connection is effected by the use of wirebond techniques, in which the parameters of the wirebond are controlled, so that less bonding force retains the leadwires to the bondpads than the attachment strength of the bondpads to the die. The wirebond techniques include attaching leadwires to bondpads on the die, using ultrasonic wedge bonding. The strength of the bond between the leadwires is significantly less than the attachment strength of the bondpads, preferably by a ratio which ensures that the bondpads are not lifted from the die when the leadwires are removed by breaking the bond between the leadwires and the bondpads. Subsequent to testing and burnin, the bond between the leadwires and the bondpads is severed. The die are then removed from the package body and the bondpads may then be attached by conventional means. The technique is useful in providing known good die.

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First Claim

Related Publications

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Patent Owner(s)

Patent OwnerAddressTotal Patents
ROUND ROCK RESEARCH, LLCBOISE, ID3576
PAPPAS, LIA M.BOISE, ID1

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Farnworth, Warren M Nampa, ID 907 23428
Gochnour, Derek J Boise, ID 52 604
Kinsman, Larry D Kuna, ID 215 3698
Wood, Alan G Boise, ID 449 15772

Cited Art

Patent Info (Count) # Cites Year
 
AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. (3)
4,855,672 Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same 26 1987
4,842,662 Process for bonding integrated circuit components 62 1988
5,086,269 Burn-in process and apparatus 36 1991
 
MICRON TECHNOLOGY, INC. (3)
4,760,335 Large scale integrated circuit test system 33 1985
4,899,107 Discrete die burn-in for nonpackaged die 195 1988
5,109,320 System for connecting integrated circuit dies to a printed wiring board 47 1990
 
AUTOMATED ELECTRONIC TECHNOLOGY, INC. (2)
4,675,599 Testsite system 14 1985
4,739,257 Testsite system 56 1986
 
AVAGO TECHNOLOGIES ECBU IP (SINGAPORE) PTE. LTD. (2)
5,008,614 TAB frame and process of testing same 38 1988
4,987,365 Method and apparatus for testing integrated circuits 22 1989
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
4,956,605 Tab mounted chip burn-in apparatus 25 1989
4,932,883 Elastomeric connectors for electronic packaging and testing 64 1989
 
RAYTHEON COMPANY (2)
4,843,313 Integrated circuit package carrier and test device 47 1984
4,783,719 Test connector for electrical devices 104 1987
 
AETRIUM INCORPORATED (1)
4,970,460 Controlled impedance testsite 19 1987
 
AMP INCORPORATED (1)
4,725,918 Protective insert for chip carriers 19 1986
 
ANALOG DEVICES, INC. (1)
4,683,423 Leadless chip test socket 17 1985
 
ASECO CORPORATION 01752 (1)
4,686,468 Contact set for test apparatus for testing integrated circuit package 21 1984
 
BELL TELEPHONE LABORATORIES, INCORPORATED (1)
4,288,841 Double cavity semiconductor chip carrier 243 1979
 
ENERGY CONVERSION DEVICES, INC. (1)
5,008,617 Functional testing of ultra large area, ultra large scale integrated circuits 36 1989
 
FUJITSU LIMITED (1)
4,859,614 Method for manufacturing semiconductor device with leads adhered to supporting insulator sheet 25 1987
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
4,954,878 Method of packaging and powering integrated circuit chips and the chip assembly formed thereby 138 1989
 
ITT CORPORATION (1)
4,996,476 Test clip for surface mount device 44 1989
 
MOTOROLA, INC. (1)
4,437,718 Non-hermetically sealed stackable chip carrier package 51 1981
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
4,801,561 Method for making a pre-testable semiconductor die package 59 1987
 
RISHO KOGYO CO., LTD. (1)
4,766,371 Test board for semiconductor packages 78 1986
 
ROCKWELL INTERNATIONAL CORPORATION (1)
4,554,505 Test socket for a leadless chip carrier 59 1983
 
ROUND ROCK RESEARCH, LLC (1)
5,173,451 Soft bond for semiconductor dies 41 1992
 
ROVEC ACQUISITIONS LTD. L.L.C. (1)
5,023,189 Method of thermal balancing RF power transistor array 17 1990
 
SOCAPEX (1)
4,683,425 Integrated circuit test clip 7 1985
 
STANDARD MICROSYSTEMS CORPORATION (1)
4,324,040 Tool for removing integrated circuits from a burn-in board 14 1980
 
TEKTRONIX, INC. (1)
4,597,617 Pressure interconnect package for integrated circuits 114 1984
 
THOMSON-CSF (1)
5,002,895 Wire bonding method with a frame, for connecting an electronic component for testing and mounting 32 1989
 
TRIGON (1)
4,340,860 Integrated circuit carrier package test probe 67 1980
 
VTC INC. (1)
4,779,047 Burn-in apparatus for integrated circuits mounted on a carrier tape 20 1987

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (12)
5,570,032 Wafer scale burn-in apparatus and process 91 1993
5,487,999 Method for fabricating a penetration limited contact having a rough textured surface 160 1994
5,898,186 Reduced terminal testing system 34 1996
6,049,977 Method of forming electrically conductive pillars 15 1997
5,976,899 Reduced terminal testing system 25 1997
6,118,138 Reduced terminal testing system 28 1997
5,994,915 Reduced terminal testing system 45 1997
6,292,009 Reduced terminal testing system 35 1999
6,534,785 Reduced terminal testing system 25 2000
6,424,168 Reduced terminal testing system 26 2001
6,815,968 Reduced terminal testing system 0 2002
6,852,999 Reduced terminal testing system 5 2003
 
FUJITSU SEMICONDUCTOR LIMITED (2)
7,880,302 Semiconductor device having metal wirings of laminated structure 0 2008
8,227,337 Semiconductor device having metal wirings of laminated structure 0 2010
 
SAMSUNG ELECTRONICS CO., LTD. (2)
5,568,057 Method for performing a burn-in test 17 1995
5,940,680 Method for manufacturing known good die array having solder bumps 8 1997
 
TEXAS INSTRUMENTS INCORPORATED (2)
5,591,649 Process of removing a tape automated bonded semiconductor from bonded leads 1 1995
5,649,981 Tool and fixture for the removal of tab leads bonded to semiconductor die pads 18 1996
 
FUJITSU LIMITED (1)
5,578,525 Semiconductor device and a fabrication process thereof 53 1996
 
HONEYWELL INC. (1)
5,891,745 Test and tear-away bond pad design 16 1997