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Abstract

A variable length decoder including the cascade combination of a buffer memory for providing parallel-bit coded data in N-bit bytes, and a first barrel shifter having an R-bit input port and an R-bit output port (R>N). The R-bit output port of the first barrel shifter is coupled to respective first inputs of a bank of R two-input OR gates. The outputs of the OR gates are coupled to the parallel input of a register or latch, the output of which is coupled to the address input port of a lookup table for providing decoded versions of variable length codewords applied to its address port, and providing indicia which indicates the length of respective decoded variable length codewords. The output of the register is also coupled to the input of a second R-bit input R-bit output second barrel shifter. The output of the second barrel shifter is coupled to respective second input connections of said bank of OR gates. The indicia provided by the lookup table are applied to a Shift State Machine, which generates control signals to control the respective bit shift operations of the first and second barrel shifters. The combination of barrel shifters and the OR circuit provide for rapid application of successive variable length codewords to the lookup table.

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First Claim