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Abstract

In an integrated circuit, a multiplexor receives incoming data at a first rate and is controllable by a high rate clock signal to output that data serially at a second, higher rate. A processing device receives the data from the multiplexor at the higher rate and is controllable by a high rate clock signal to process that data. Clock generation circuitry receives a first clock signal at the first rate and produces the high rate signal for the processing device and the multiplexor. Clock generation circuitry includes sequentially connected delay devices, one connected to receive the first clock signal. Each delay device produces a trigger signal and an output signal a predetermined time after receiving the trigger signal from the previous delay device. A control circuit is common to the delay devices for controlling the predetermined time interval. An output circuit receives the output signals of the delay devices and produces the high rate clock signal.

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First Claim