Method and apparatus for controlling dual bus system

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United States of America Patent

PATENT NO 5345566
SERIAL NO

07825063

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Abstract

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A method and apparatus for controlling a dual bus system, capable of realizing high speed and continuous operation even if one of the buses of the dual bus system fails. The method and apparatus has a dual bus system, a plurality of electronic circuits connected to both buses of the dual bus system, and bus controller for providing a bus use allowance signal to one of the plurality of electronic circuits, the one electronic circuit being selected in accordance with bus occupation request signals issued from the plurality of electronic circuits requesting data transfer. If the bus occupation request signals for both buses of the dual bus system originates from the one selected electronic circuit and the outputs of the arbiters coincide, the bus use allowance signal is provided to the one selected electronic circuit for the allowance of occupying both buses of the dual bus system. A completion of data transfer at the dual bus system is determined when data transfer is completed at both buses. Continuous operation can be ensured immediately upon occurrence of a failure, and high speed operation of a computer system is possible.

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Patent Owner(s)

Patent OwnerAddress
HITACHI LTD A CORP OF JAPAN6 KANDA SURUGADAI 4-CHOME CHIYODA-KU TOKYO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fukumaru, Hiroaki Hitachi, JP 9 207
Masui, Koji Hitachi, JP 10 123
Miyazaki, Yoshihiro Hitachi, JP 28 497
Ogawa, Hisao Hitachi, JP 37 245
Tanji, Masayuki Hitachi, JP 10 216
Yamaguchi, Syoji Hitachi, JP 9 269

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