High speed burst read address generation with high speed transfer
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 6, 1994
Grant Date -
N/A
app pub date -
Oct 4, 1991
filing date -
Oct 4, 1991
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set of address sequences as a function of the states of these bits. A first predetermined address bit is used to select different sequences of addressed readout data words to be transferred by the pair of DRAMs to the user. A second predetermined address bit is complemented to reverse two high order addressed word responses with two low order addressed word responses of specific address sequences. These operations are utilized in all of the required address sequences within different subgroups.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully