System for interconnecting VLSI circuits with transmission line characteristics
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 13, 1994
Grant Date -
N/A
app pub date -
Jan 14, 1993
filing date -
Jan 14, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
This invention provides a means to interconnect high performance CMOS VLSI circuits. LTL (a coined descriptor for describing a novel CMOS interface standard) offers improved performance by providing active threshold control of an input buffer to speed signal capture, and by controlling performance limiting characteristics of signal reflection, ground bounce, receiver overdriving and ringing. These performance limiting characteristics are controlled by providing: level-sensitive impedance control of an output driver, distributed active line termination using impedances of input buffers on a transmission line, and balanced loading using closed-loop transmission lines.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully