Row redundancy circuit sharing a fuse box
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 20, 1994
Grant Date -
N/A
app pub date -
Jul 13, 1993
filing date -
Jul 13, 1992
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
The present invention discloses a row redundancy circuit in which, when the number of word lines containing defective memory cells in a first normal memory cell array is greater than the number of redundant word lines in a first redundant memory cell array, an adjacent redundant row address decoder and associated adjacent redundant word lines are used to repair such excess number of defects. Therefore, there is no need to increase the number of redundant row address decoders and redundancy efficiency is greatly increased.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully