Data processor having logical address memories and purge capabilities
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United States of America Patent
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Sep 20, 1994
Issued Date -
N/A
app pub date -
Apr 3, 1990
filing date -
Mar 17, 1986
priority date (Note) -
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Abstract
A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.
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