Method for forming interconnect structures for integrated circuits

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5354712
SERIAL NO

07974760

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method is provided for forming interconnect structures for ULSI integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the sidewalls and bottom of interconnect trenches defined in a dielectric layer, and a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench. Advantageously, the metal layer forming interconnect comprises a layer of copper which is deposited by chemical vapour deposition from an organo-metallic precursor at low temperature. Etching back and planarization of the barrier layer and the metal layer is accomplished by chemical mechanical polishing. Second and subsequent levels of metallization are provided by repeating the process steps, as required, to provide another dielectric layer defining interconnect trenches, selectively lining the trenches with a conformal barrier layer and then filling the trenches with selective deposition of a conformal conductive layer of metal, with planarization of the resulting conformal layers by chemical mechanical polishing. Preferably, via holes forming contacts to underlying device structures are filled with copper or tungsten.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
NORTEL NETWORKS LIMITEDMONTREAL QUEBEC90

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Emesh, Ismail T Cumberland, CA 26 1014
Ho, Yu Q Kanata, CA 1 312
Jolly, Gurvinder Orleans, CA 6 628

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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* Cited By Examiner

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Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (9)
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HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (2)
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7911060 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 0 2009
* 2010/0078,827 MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION 2 2009
8110495 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 0 2011
* 2011/0129,995 MULTILAYER WIRING STRUCTURE OF SEMICONDUCTOR DEVICE, METHOD OF PRODUCING SAID MULTILAYER WIRING STRUCTURE AND SEMICONDUCTOR DEVICE TO BE USED FOR RELIABILITY EVALUATION 0 2011
 
HSBC BANK USA (2)
* 2003/0038,647 Probe card for probing wafers with raised contact elements 2 2002
* 2004/0198,081 Microelectronic spring contact elements 5 2004
 
APPLIED MATERIALS, INC. (52)
* 5877087 Low temperature integrated metallization process and apparatus 35 1995
* 6066358 Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer 30 1996
* 6077781 Single step process for blanket-selective CVD aluminum deposition 8 1996
* 6001420 Semi-selective chemical vapor deposition 56 1996
* 6537905 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 16 1996
* 6139697 Low temperature integrated via and trench fill process and apparatus 76 1997
* 6139905 Integrated CVD/PVD Al planarization using ultra-thin nucleation layers 9 1997
6605197 Method of sputtering copper to fill trenches and vias 25 1997
* 5877086 Metal planarization using a CVD wetting film 33 1997
* 5989623 Dual damascene metallization 108 1997
6184137 Structure and method for improving low temperature copper reflow in semiconductor features 25 1998
6355560 Low temperature integrated metallization process and apparatus 6 1998
6726776 Low temperature integrated metallization process and apparatus 4 1999
6430458 Semi-selective chemical vapor deposition 8 1999
6207222 Dual damascene metallization 73 1999
6207558 Barrier applications for aluminum planarization 42 1999
6458684 Single step process for blanket-selective CVD aluminum deposition 33 2000
6627542 Continuous, non-agglomerated adhesion of a seed layer to a barrier layer 25 2000
6562715 Barrier layer structure for copper metallization and method of forming the structure 44 2000
6436267 Method for achieving copper fill of high aspect ratio interconnect features 47 2000
6753258 Integration scheme for dual damascene structure 14 2000
* 6566259 Integrated deposition process for copper metallization 17 2000
6352926 Structure for improving low temperature copper reflow in semiconductor features 6 2000
6391776 Method of depositing a copper seed layer which promotes improved feature surface coverage 13 2001
* 6368880 Barrier applications for aluminum planarization 13 2001
6758947 Damage-free sculptured coating deposition 33 2001
6559061 Method and apparatus for forming improved metal interconnects 40 2001
* 6790776 Barrier layer for electroplating processes 26 2001
* 2002/0060,363 Reliability barrier integration for Cu application 12 2002
6500762 Method of depositing a copper seed layer which promotes improved feature surface coverage 38 2002
6709987 Method and apparatus for forming improved metal interconnects 34 2002
6743714 Low temperature integrated metallization process and apparatus 1 2002
6797620 Method and apparatus for improved electroplating fill of an aperture 4 2002
* 2003/0194,850 Method and apparatus for improved electroplating fill of an aperture 7 2002
* 2003/0013,297 Reliability barrier integration for Cu application 2 2002
6878620 Side wall passivation films for damascene cu/low k electronic devices 6 2002
* 2004/0092,095 Side wall passivation films for damascene cu/low k electronic devices 3 2002
7112528 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 4 2003
* 2003/0161,943 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 1 2003
6793779 Sputtering method for filling holes with copper 1 2003
6881673 Integrated deposition process for copper metallization 2 2003
6992012 Method and apparatus for forming improved metal interconnects 24 2004
6919275 Method of preventing diffusion of copper through a tantalum-comprising barrier layer 58 2004
* 2004/0209,460 Reliability barrier integration for Cu application 48 2004
* 2005/0031,784 Barrier layer for electroplating processes 0 2004
7074714 Method of depositing a metal seed layer on semiconductor substrates 23 2004
7253109 Method of depositing a tantalum nitride/tantalum diffusion barrier layer system 33 2005
7381639 Method of depositing a metal seed layer on semiconductor substrates 6 2006
9390970 Method for depositing a diffusion barrier layer and a metal conductive layer 0 2007
7687909 Metal / metal nitride barrier layer for semiconductor device applications 2 2007
7989343 Method of depositing a uniform metal seed layer over a plurality of recessed semiconductor features 1 2010
8158511 Method of depositing a uniform barrier layer and metal seed layer with reduced overhang over a plurality of recessed semiconductor features 0 2011
 
KAWASAKI MICROELECTRONICS, INC. (1)
* 5486492 Method of forming multilayered wiring structure in semiconductor device 79 1993
 
TEPLITSKY, ALEXANDER ARKADIEVICH (1)
* 2009/0032,383 METHOD AND DEVICE FOR PRODUCING COKE FROM NONCAKING COALS 0 2007
* Cited By Examiner