US Patent No: 5,354,712

Number of patents in Portfolio can not be more than 2000

Method for forming interconnect structures for integrated circuits

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Abstract

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A method is provided for forming interconnect structures for ULSI integrated circuits. Preferably, a barrier layer of a conductive material which forms a seed layer for metal deposition is provided selectively on the sidewalls and bottom of interconnect trenches defined in a dielectric layer, and a conformal layer of metal is selectively deposited on the barrier layer within the interconnect trench. Advantageously, the metal layer forming interconnect comprises a layer of copper which is deposited by chemical vapour deposition from an organo-metallic precursor at low temperature. Etching back and planarization of the barrier layer and the metal layer is accomplished by chemical mechanical polishing. Second and subsequent levels of metallization are provided by repeating the process steps, as required, to provide another dielectric layer defining interconnect trenches, selectively lining the trenches with a conformal barrier layer and then filling the trenches with selective deposition of a conformal conductive layer of metal, with planarization of the resulting conformal layers by chemical mechanical polishing. Preferably, via holes forming contacts to underlying device structures are filled with copper or tungsten.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
NORTEL NETWORKS LIMITEDMONTREAL QUEBEC1742

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Emesh, Ismail T Gilbert, AZ 18 895
Ho, Yu Q Kanata, CA 1 294
Jolly, Gurvinder Laguna Niguel, CA 6 577

Cited Art Landscape

Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (2)
5,124,780 Conductive contact plug and a method of forming a conductive contact plug in an integrated circuit using laser planarization 90 1991
5,225,034 Method of chemical mechanical polishing predominantly copper containing metal layers in semiconductor processing 192 1992
 
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1)
5,084,413 Method for filling contact hole 36 1990
 
MOTOROLA, INC. (1)
4,822,753 Method for making a w/tin contact 88 1988
 
NXP B.V. (1)
5,063,175 Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material 56 1988
 
SAMSUNG ELECTRONICS CO., LTD. (1)
5,091,339 Trenching techniques for forming vias and channels in multilayer electrical interconnects 105 1990
 
SHARP KABUSHIKI KAISHA (1)
5,219,789 Method for forming contact portion of semiconductor device 28 1992
 
STMICROELECTRONICS N.V. (1)
4,954,214 Method for making interconnect structures for VLSI devices 39 1989

Patent Citation Ranking

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Patent Info (Count) # Cites Year
 
MICRON TECHNOLOGY, INC. (46)
6,083,831 Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor 37 1996
5,956,612 Trench/hole fill processes for semiconductor fabrication 35 1996
6,037,248 Method of fabricating integrated circuit wiring with low RC time delay 92 1997
6,331,725 Integrated circuitry 4 1997
6,211,073 Methods for making copper and other metal interconnections in integrated circuits 41 1998
6,284,655 Method for producing low carbon/oxygen conductive layers 49 1998
6,300,213 Semiconductor processing methods of forming a storage node of a capacitor 5 1998
6,329,286 Methods for forming conformal iridium layers on substrates 32 1999
6,297,156 Method for enhanced filling of high aspect ratio dual damascene structures 5 1999
6,633,074 Integrated circuit wiring with low RC time delay 4 1999
6,323,511 Structures including low carbon/oxygen conductive layers 48 1999
7,262,130 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals 9 2000
6,312,984 Semiconductor processing method of forming a contact pedestal of forming a storage node of a capacitor and integrated circuitry 2 2000
6,690,055 Devices containing platinum-rhodium layers and methods 18 2000
6,660,631 Devices containing platinum-iridium films and methods of preparing such films and devices 30 2000
6,426,292 Methods for forming iridium and platinum containing films on substrates 36 2001
6,984,891 Methods for making copper and other metal interconnections in integrated circuits 29 2001
6,495,458 Method for producing low carbon/oxygen conductive layers 46 2001
6,403,414 Method for producing low carbon/oxygen conductive layers 64 2001
6,498,375 Integrated circuitry 2 2001
6,743,641 Method of improving surface planarity prior to MRAM bit material deposition 18 2001
7,105,914 Integrated circuit and seed layers 15 2002
7,378,737 Structures and methods to enhance copper metallization 5 2002
7,301,190 Structures and methods to enhance copper metallization 6 2002
6,743,716 Structures and methods to enhance copper metallization 12 2002
6,756,301 Method of forming a metal seed layer for subsequent plating 1 2002
7,220,665 H.sub.2 plasma treatment 12 2003
6,900,107 Devices containing platinum-iridium films and methods of preparing such films and devices 12 2003
7,271,085 Method of fabricating a semiconductor interconnect structure 2 2003
7,067,421 Multilevel copper interconnect with double passivation 11 2003
7,375,388 Device having improved surface planarity prior to MRAM bit material deposition 0 2003
7,226,861 Methods and apparatus for forming rhodium-containing layers 4 2004
7,394,157 Integrated circuit and seed layers 8 2004
8,779,596 Structures and methods to enhance copper metallization 0 2004
7,943,505 Advanced VLSI metallization 1 2004
7,217,970 Devices containing platinum-iridium films and methods of preparing such films and devices 8 2004
7,262,505 Selective electroless-plated copper metallization 19 2004
7,253,521 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals 9 2004
7,402,879 Layered magnetic structures having improved surface planarity for bit material deposition 0 2005
7,504,674 Electronic apparatus having a core conductive structure within an insulating layer 5 2005
7,402,516 Method for making integrated circuits 3 2006
7,535,103 Structures and methods to enhance copper metallization 7 2006
7,368,378 Methods for making integrated-circuit wiring from copper, silver, gold, and other metals 4 2006
7,393,785 Methods and apparatus for forming rhodium-containing layers 23 2007
8,565,016 System having improved surface planarity for bit material deposition 0 2008
7,745,934 Integrated circuit and seed layers 3 2008
 
APPLIED MATERIALS, INC. (44)
5,877,087 Low temperature integrated metallization process and apparatus 35 1995
6,066,358 Blanket-selective chemical vapor deposition using an ultra-thin nucleation layer 30 1996
6,077,781 Single step process for blanket-selective CVD aluminum deposition 8 1996
6,001,420 Semi-selective chemical vapor deposition 50 1996
6,537,905 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 13 1996
6,139,697 Low temperature integrated via and trench fill process and apparatus 72 1997
6,139,905 Integrated CVD/PVD Al planarization using ultra-thin nucleation layers 5 1997
6,605,197 Method of sputtering copper to fill trenches and vias 23 1997
5,877,086 Metal planarization using a CVD wetting film 33 1997
5,989,623 Dual damascene metallization 106 1997
6,184,137 Structure and method for improving low temperature copper reflow in semiconductor features 22 1998
6,355,560 Low temperature integrated metallization process and apparatus 6 1998
6,726,776 Low temperature integrated metallization process and apparatus 4 1999
6,430,458 Semi-selective chemical vapor deposition 6 1999
6,207,222 Dual damascene metallization 70 1999
6,207,558 Barrier applications for aluminum planarization 40 1999
6,458,684 Single step process for blanket-selective CVD aluminum deposition 15 2000
6,627,542 Continuous, non-agglomerated adhesion of a seed layer to a barrier layer 18 2000
6,562,715 Barrier layer structure for copper metallization and method of forming the structure 33 2000
6,436,267 Method for achieving copper fill of high aspect ratio interconnect features 44 2000
6,753,258 Integration scheme for dual damascene structure 14 2000
6,566,259 Integrated deposition process for copper metallization 16 2000
6,352,926 Structure for improving low temperature copper reflow in semiconductor features 5 2000
6,391,776 Method of depositing a copper seed layer which promotes improved feature surface coverage 12 2001
6,368,880 Barrier applications for aluminum planarization 13 2001
6,758,947 Damage-free sculptured coating deposition 28 2001
6,559,061 Method and apparatus for forming improved metal interconnects 35 2001
6,790,776 Barrier layer for electroplating processes 20 2001
6,500,762 Method of depositing a copper seed layer which promotes improved feature surface coverage 33 2002
6,709,987 Method and apparatus for forming improved metal interconnects 29 2002
6,743,714 Low temperature integrated metallization process and apparatus 1 2002
6,797,620 Method and apparatus for improved electroplating fill of an aperture 4 2002
6,878,620 Side wall passivation films for damascene cu/low k electronic devices 6 2002
7,112,528 Fully planarized dual damascene metallization using copper line interconnect and selective CVD aluminum plug 4 2003
6,793,779 Sputtering method for filling holes with copper 0 2003
6,881,673 Integrated deposition process for copper metallization 1 2003
6,992,012 Method and apparatus for forming improved metal interconnects 18 2004
6,919,275 Method of preventing diffusion of copper through a tantalum-comprising barrier layer 45 2004
7,074,714 Method of depositing a metal seed layer on semiconductor substrates 19 2004
7,253,109 Method of depositing a tantalum nitride/tantalum diffusion barrier layer system 28 2005
7,381,639 Method of depositing a metal seed layer on semiconductor substrates 2 2006
7,687,909 Metal / metal nitride barrier layer for semiconductor device applications 2 2007
7,989,343 Method of depositing a uniform metal seed layer over a plurality of recessed semiconductor features 1 2010
8,158,511 Method of depositing a uniform barrier layer and metal seed layer with reduced overhang over a plurality of recessed semiconductor features 0 2011
 
FormFactor, Inc. (31)
6,482,013 Microelectronic spring contact element and electronic component having a plurality of spring contact elements 147 1997
6,043,563 Electronic components with terminals and spring contact elements extending from areas which are remote from the terminals 165 1997
6,520,778 Microelectronic contact structures, and methods of making same 152 1998
6,268,015 Method of making and using lithographic contact springs 124 1998
6,255,126 Lithographic contact elements 186 1998
6,672,875 Spring interconnect structures 106 1999
6,491,968 Methods for making spring interconnect structures 100 1999
7,714,235 Lithographically defined microelectronic contact structures 6 2000
6,727,580 Microelectronic spring contact elements 77 2000
7,073,254 Method for mounting a plurality of spring contact elements 26 2000
6,475,822 Method of making microelectronic contact structures 89 2000
6,791,176 Lithographic contact elements 78 2001
6,616,966 Method of making lithographic contact springs 125 2001
7,086,149 Method of making a contact structure with a distinctly formed tip structure 17 2001
6,624,648 Probe card assembly 111 2001
6,615,485 Probe card assembly and kit, and methods of making same 88 2001
6,807,734 Microelectronic contact structures, and methods of making same 78 2002
7,122,760 Using electric discharge machining to manufacture probes 2 2002
6,945,827 Microelectronic contact structure 40 2002
7,371,072 Spring interconnect structures 5 2003
7,579,269 Microelectronic spring contact elements 3 2004
7,287,322 Lithographic contact elements 14 2004
7,731,546 Microelectronic contact structure 2 2005
7,601,039 Microelectronic contact structure and method of making same 12 2006
7,488,917 Electric discharge machining of a probe array 0 2006
7,555,836 Method of making lithographic contact elements 6 2007
7,553,165 Spring interconnect structures 8 2008
7,841,863 Spring interconnect structures 1 2009
7,798,822 Microelectronic contact structures 1 2009
8,373,428 Probe card assembly and kit, and methods of making same 7 2009
8,033,838 Microelectronic contact structure 3 2009
 
LITTELFUSE, INC. (18)
7,446,030 Methods for fabricating current-carrying structures using voltage switchable dielectric materials 19 2004
7,923,844 Semiconductor devices including voltage switchable materials for over-voltage protection 7 2006
7,825,491 Light-emitting device using voltage switchable dielectric material 1 2006
7,695,644 Device applications for voltage switchable dielectric material having high aspect ratio particles 5 2007
7,872,251 Formulations for voltage switchable dielectric material having a stepped voltage response and methods for making the same 7 2007
7,793,236 System and method for including protective voltage switchable dielectric material in the design or simulation of substrate devices 3 2007
8,206,614 Voltage switchable dielectric material having bonded particle constituents 0 2009
8,203,421 Substrate device or package using embedded layer of voltage switchable dielectric material in a vertical switching configuration 0 2009
8,362,871 Geometric and electric field considerations for including transient protective material in substrate devices 0 2009
8,399,773 Substrates having voltage switchable dielectric materials 0 2010
7,981,325 Electronic device for voltage switchable dielectric material having high aspect ratio particles 0 2010
7,968,010 Method for electroplating a substrate 2 2010
7,968,014 Device applications for voltage switchable dielectric material having high aspect ratio particles 0 2010
7,968,015 Light-emitting diode device for voltage switchable dielectric material having high aspect ratio particles 0 2010
8,163,595 Formulations for voltage switchable dielectric materials having a stepped voltage response and methods for making the same 1 2010
8,117,743 Methods for fabricating current-carrying structures using voltage switchable dielectric materials 0 2010
8,272,123 Substrates having voltage switchable dielectric materials 0 2011
8,310,064 Semiconductor devices including voltage switchable materials for over-voltage protection 0 2011
 
CVC PRODUCTS, INC. (12)
6,461,675 Method for forming a copper film on a substrate 34 1998
6,294,836 Semiconductor chip interconnect barrier material and fabrication method 82 1998
6,245,655 Method for planarized deposition of a material 17 1999
6,692,575 Apparatus for supporting a substrate in a reaction chamber 12 2000
6,544,341 System for fabricating a device on a substrate with a process gas 8 2000
6,508,197 Apparatus for dispensing gas for fabricating substrates 16 2000
6,274,495 Method for fabricating a device on a substrate 13 2000
6,365,502 Microelectronic interconnect material with adhesion promotion layer and fabrication method 81 2000
6,812,126 Method for fabricating a semiconductor chip interconnect 29 2000
6,444,263 Method of chemical-vapor deposition of a material 47 2000
6,645,847 Microelectronic interconnect material with adhesion promotion layer and fabrication method 31 2002
6,627,995 Microelectronic interconnect material with adhesion promotion layer and fabrication method 36 2002
 
ADVANCED MICRO DEVICES, INC. (11)
5,625,231 Low cost solution to high aspect ratio contact/via adhesion layer application for deep sub-half micrometer back-end-of line technology 9 1995
6,013,574 Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines 28 1997
6,056,864 Electropolishing copper film to enhance CMP throughput 54 1998
6,291,339 Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same 9 1999
6,291,887 Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer 20 1999
6,153,514 Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer 20 1999
6,235,628 Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer 30 1999
6,207,576 Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide etch stop layer 12 1999
6,380,091 Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer 5 1999
6,207,577 Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer 15 1999
6,433,402 Selective copper alloy deposition 14 2000
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (11)
5,707,893 Method of making a circuitized substrate using two different metallization processes 12 1995
5,976,970 Method of making and laterally filling key hole structure for ultra fine pitch conductor lines 18 1996
5,940,729 Method of planarizing a curved substrate and resulting structure 17 1996
6,121,129 Method of contact structure formation 13 1997
6,028,004 Process for controlling the height of a stud intersecting an interconnect 1 1998
6,181,012 Copper interconnection structure incorporating a metal seed layer 163 1998
6,150,255 Method of planarizing a curved substrate and resulting structure 6 1999
6,413,854 Method to build multi level structure 18 1999
6,399,496 Copper interconnection structure incorporating a metal seed layer 41 2000
8,004,060 Metal gate compatible electrical antifuse 2 2007
7,906,428 Modified via bottom structure for reliability enhancement 0 2008
 
ROUND ROCK RESEARCH, LLC (10)
6,288,442 Integrated circuit with oxidation-resistant polymeric layer 46 1998
6,211,049 Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals 27 1999
6,208,016 Forming submicron integrated-circuit wiring from gold, silver, copper and other metals 22 1999
6,849,927 Forming submicron integrated-circuit wiring from gold, silver, copper, and other metals 8 2001
6,552,432 Mask on a polymer having an opening width less than that of the opening in the polymer 12 2001
7,091,611 Multilevel copper interconnects with low-k dielectrics and air gaps 23 2002
6,756,298 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals 64 2002
6,995,470 Multilevel copper interconnects with low-k dielectrics and air gaps 7 2004
7,285,196 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals 9 2004
7,670,469 Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals 1 2007
 
SEED LAYERS TECHNOLOGY LLC (10)
6,610,151 Seed layers for interconnects and methods and apparatus for their fabrication 22 2000
6,518,668 Multiple seed layers for metallic interconnects 26 2000
6,924,226 Methods for making multiple seed layers for metallic interconnects 9 2002
6,903,016 Combined conformal/non-conformal seed layers for metallic interconnects 16 2003
7,105,434 Advanced seed layery for metallic interconnects 3 2004
7,199,052 Seed layers for metallic interconnects 9 2005
7,682,496 Apparatus for depositing seed layers 1 2006
7,282,445 Multiple seed layers for interconnects 3 2007
7,550,386 Advanced seed layers for interconnects 0 2007
8,123,861 Apparatus for making interconnect seed layers and products 0 2010
 
INTEL CORPORATION (8)
5,714,418 Diffusion barrier for electrical interconnects in an integrated circuit 59 1995
5,604,158 Integrated tungsten/tungsten silicide plug process 23 1996
5,977,634 Diffusion barrier for electrical interconnects in an integrated circuit 3 1997
6,169,024 Process to manufacture continuous metal interconnects 42 1998
6,037,255 Method for making integrated circuit having polymer interlayer dielectric 32 1999
7,166,922 Continuous metal interconnects 0 2000
8,258,057 Copper-filled trench contact for transistor performance improvement 4 2006
8,766,372 Copper-filled trench contact for transistor performance improvement 0 2012
 
Microfabrica Inc. (7)
7,412,767 Microprobe tips and methods for making 5 2005
7,363,705 Method of making a contact 7 2005
7,273,812 Microprobe tips and methods for making 6 2005
8,717,055 Probe devices formed from multiple planar layers of structural material with tip regions formed from one or more intermediate planar layers 0 2011
8,729,916 Methods of creating probe structures from a plurality of planar layers 0 2011
8,723,543 Methods of creating probe structures from a plurality of planar layers 0 2011
8,717,054 Methods of creating probe structures from a plurality of planar layers 0 2011
 
GLOBALFOUNDRIES INC. (6)
5,851,913 Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process 3 1996
5,968,333 Method of electroplating a copper or copper alloy interconnect 103 1998
6,127,282 Method for removing copper residue from surfaces of a semiconductor wafer 11 1998
6,287,968 Method of defining copper seed layer for selective electroless plating processing 27 1999
6,255,735 Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers 10 1999
6,472,317 Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers 22 2001
 
RPX CORPORATION (6)
6,815,338 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 0 2003
7,148,572 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 1 2004
7,443,031 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 1 2006
7,642,654 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor to be used for reliability evaluation 0 2008
7,911,060 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 0 2009
8,110,495 Multilayer wiring structure of semiconductor device, method of producing said multilayer wiring structure and semiconductor device to be used for reliability evaluation 0 2011
 
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (5)
5,948,700 Method of planarization of an intermetal dielectric layer using chemical mechanical polishing 19 1996
5,693,563 Etch stop for copper damascene process 204 1996
6,261,954 Method to deposit a copper layer 6 2000
6,368,958 Method to deposit a cooper seed layer for dual damascence interconnects 2 2001
6,876,080 Etch stop for copper damascene process 0 2002
 
LAM RESEARCH CORPORATION (5)
6,165,956 Methods and apparatus for cleaning semiconductor substrates after polishing of copper film 27 1997
6,593,282 Cleaning solutions for semiconductor substrates after polishing of copper film 7 1998
6,162,301 Methods and apparatus for cleaning semiconductor substrates after polishing of copper film 28 1999
6,479,443 Cleaning solution and method for cleaning semiconductor substrates after polishing of copper film 3 2000
6,303,551 Cleaning solution and method for cleaning semiconductor substrates after polishing of cooper film 33 2000
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (5)
5,663,108 Optimized metal pillar via process 32 1996
5,895,975 Optimized process for creating and passivating a metal pillar via structure located between two metal interconnect structures 7 1997
6,228,760 Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish 23 1999
6,524,950 Method of fabricating copper damascene 14 2000
6,458,689 Use of PE-SiON or PE-Oxide for contact or via photo and for defect reduction with oxide and w chemical-mechanical polish 11 2001
 
CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC. (4)
6,316,356 Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication 4 1998
6,323,081 Diffusion barrier layers and methods of forming same 40 1998
6,774,035 Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication 4 2001
6,784,550 Thermal processing of metal alloys for an improved CMP process in integrated circuit fabrication 1 2001
 
SAMSUNG ELECTRONICS CO., LTD. (4)
5,604,156 Wire forming method for semiconductor device 51 1995
6,635,582 Method of manufacturing semiconductor device 5 1999
6,680,538 Semiconductor device for suppressing detachment of conductive layer 6 2001
6,645,849 Method for manufacturing semiconductor device for suppressing detachment of conductive layer 0 2002
 
ALTERA CORPORATION (3)
5,998,295 Method of forming a rough region on a substrate 6 1996
6,002,182 Laser alignment target 10 1998
6,624,524 Laser alignment target 2 1999
 
FUJITSU LIMITED (3)
5,916,453 Methods of planarizing structures on wafers and substrates by polishing 18 1996
7,579,553 Front-and-back electrically conductive substrate 7 2001
6,733,685 Methods of planarizing structures on wafers and substrates by polishing 35 2001
 
FUJITSU SEMICONDUCTOR LIMITED (3)
7,358,180 Method of forming wiring structure and semiconductor device 4 2004
8,373,274 Method of forming wiring structure and semiconductor device comprising underlying refractory metal layers 1 2008
7,745,232 Semiconductor device and method of manufacturing the same 2 2008
 
TEXAS INSTRUMENTS INCORPORATED (3)
6,077,774 Method of forming ultra-thin and conformal diffusion barriers encapsulating copper 35 1997
5,891,804 Process for conductors with selective deposition 48 1997
6,706,623 Method and system for avoiding plasma etch damage 0 1999
 
APTINA IMAGING CORPORATION (2)
6,221,763 Method of forming a metal seed layer for subsequent plating 58 1999
6,489,235 Method of forming a metal seed layer for subsequent plating 8 2001
 
LSI LOGIC CORPORATION (2)
5,670,425 Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench 26 1995
5,895,261 Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench 15 1997
 
MOTOROLA, INC. (2)
5,429,989 Process for fabricating a metallization structure in a semiconductor device 19 1994
5,677,244 Method of alloying an interconnect structure with copper 41 1996
 
NANYA TECHNOLOGY CORPORATION (2)
6,284,656 Copper metallurgy in integrated circuits 31 1998
6,614,099 Copper metallurgy in integrated circuits 34 2001
 
SHARP KABUSHIKI KAISHA (2)
5,744,394 Method for fabricating a semiconductor device having copper layer 51 1997
6,204,176 Substituted phenylethylene precursor deposition method 2 1999
 
TESSERA ADVANCED TECHNOLOGIES, INC. (2)
6,589,863 Semiconductor device and manufacturing method thereof 22 1999
7,045,898 Semiconductor device and manufacturing method thereof 0 2003
 
UNITED MICROELECTRONICS CORP. (2)
6,008,118 Method of fabricating a barrier layer 13 1998
6,521,523 Method for forming selective protection layers on copper interconnects 20 2001
 
ADVANCED TECHNOLOGY MATERIALS, INC. (1)
6,322,600 Planarization compositions and methods for removing interlayer dielectric films 30 1998
 
AEROFLEX COLORADO SPRINGS INC. (1)
6,069,078 Multi-level interconnect metallization technique 9 1997
 
ANELVA CORPORATION (1)
6,387,444 Single substrate processing CVD procedure for depositing a metal film using first and second CVD processes in first and second process chambers 1 2000
 
COHEN, URI (1)
8,586,471 Seed layers for metallic interconnects and products 0 2012
 
CONTEX, INC. (1)
6,115,233 Integrated circuit device having a capacitor with the dielectric peripheral region being greater than the dielectric central region 40 1996
 
FELLOWS RESEARCH B.V., LLC (1)
5,976,928 Chemical mechanical polishing of FeRAM capacitors 111 1997
 
Formfactor, et al. (1)
6,937,037 Probe card assembly for contacting a device with raised contact elements 62 2002
 
FREESCALE SEMICONDUCTOR, INC. (1)
6,077,768 Process for fabricating a multilevel interconnect 12 1996
 
GEORGIA TECH RESEARCH CORPORATION (1)
6,261,941 Method for manufacturing a multilayer wiring substrate 13 1999
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
7,795,138 Method of depositing a metal seed layer over recessed feature surfaces in a semiconductor substrate 0 2009
 
INFINEON TECHNOLOGIES AG (1)
6,613,664 Barbed vias for electrical and mechanical connection between conductive layers in semiconductor devices 33 2000
 
KABUSHIKI KAISHA TOSHIBA (1)
5,950,099 Method of forming an interconnect 3 1996
 
KAWASAKI MICROELECTRONICS, INC. (1)
5,486,492 Method of forming multilayered wiring structure in semiconductor device 77 1993
 
LG SEMICON CO., LTD. (1)
5,547,901 Method for forming a copper metal wiring with aluminum containing oxidation barrier 18 1995
 
NATIONAL SEMICONDUCTOR CORPORATION (1)
6,140,238 Self-aligned copper interconnect structure and method of manufacturing same 69 1999
 
NEC ELECTRONICS CORPORATION (1)
6,040,240 Method for forming interconnection structure 5 1999
 
NEWPORT FAB, LLC (1)
6,255,192 Methods for barrier layer formation 10 1998
 
QIMONDA AG (1)
6,486,049 Method of fabricating semiconductor devices with contact studs formed without major polishing defects 2 2001
 
RENESAS ELECTRONICS CORPORATION (1)
6,387,821 Method of manufacturing a semiconductor device 4 1999
 
SHINKO ELECTRIC INDUSTRIES CO., LTD. (1)
7,114,251 Method of producing of circuit board; for semiconductor device 10 2002
 
SONY CORPORATION (1)
6,380,065 Interconnection structure and fabrication process therefor 28 1999
 
STMICROELECTRONICS, INC. (1)
5,856,707 Vias and contact plugs with an aspect ratio lower than the aspect ratio of the structure in which they are formed 22 1996
 
SYMBIOS LOGIC INC. (1)
6,010,963 Global planarization using SOG and CMP 5 1995
 
TEXAS INSTRUMENTS-ACER INCORPORATED (1)
5,976,967 Dual damascene process for multi-level metallization and interconnection structure 4 1998
 
WEBER-STEPHEN PRODUCTS CO. (1)
6,417,090 Damascene arrangement for metal interconnection using low k dielectric constant materials for etch stop layer 7 1999