TTL to CMOS translator circuit and method
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United States of America Patent
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Oct 11, 1994
Grant Date -
N/A
app pub date -
Mar 24, 1993
filing date -
Mar 24, 1993
priority date (Note) -
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Abstract
A high speed, low powered, BiCMOS TTL to CMOS translator circuit and method which relies on an internally generated reference voltage and which is capable of driving high loads. The translator circuit includes a first inverting and translating stage having a pull up transistor and a pull down transistor, a high gain stage and a second inverting stage.
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