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Abstract

A phase-lock loop circuit including a voltage-controlled oscillator for generating a clock signal. The voltage-controlled oscillator includes a plurality of multiplexers coupled in series. The signal generated by the last multiplexer in the series is used as a clock signal. Each of the multiplexers in the series has a select input. Either a first signal or a second signal propagates through the series of multiplexers, depending on a select signal applied to the select inputs of the multiplexers. The second signal is the first signal with a predetermined delay. A 3-input multiplexer is connected to the first and last multiplexers in the series to the form a ring oscillator. The first or second signals output by the last multiplexer in the series is sent to an input of the 3-input multiplexer, and a test signal is sent to a third input of the 3-input multiplexer. The 3-input multiplexer also receives the select signal and a test mode signal. If the test mode signal is asserted, the 3-input multiplexer propagates the test signal to the first multiplexer in the series. If the test mode is not asserted, the 3-input multiplexer propagates either the first or the second signals based on the select signal. The phase-lock loop circuit also includes a phase frequency detection circuit for generating a phase difference signal indicative of the phase difference between the clock signal and a reference signal, a filter for generating a control signal to the voltage-controlled oscillator in response to the phase difference signal, and a feedback divider for receiving the clock signal and for feeding back a divided clock signal to the phase frequency detection circuit.

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