Glitch-free clock multiplexer
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United States of America Patent
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Oct 18, 1994
Grant Date -
N/A
app pub date -
Dec 31, 1992
filing date -
Dec 31, 1992
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A multiplexer for selecting one of at least two input signals as the output on sensing the change in the state of a select input waits for the clock signal of the active first clock to transition to a predetermined state, disconnects the active first clock from the output of the multiplexer and maintains the output of the multiplexer in the predetermined state while waiting for the clock signal of a second clock to transition to the predetermined state. The second clock is connected as the multiplexer output while the clock signal of the second clock is in the predetermined state. In a preferred embodiment, the predetermined state is a low logic level.
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