Semiconductor integrated circuit device including a plurality of cell array blocks
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United States of America Patent
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Oct 18, 1994
Grant Date -
N/A
app pub date -
Sep 30, 1991
filing date -
Oct 5, 1990
priority date (Note) -
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Abstract
A plurality of sub chips are formed on a chip. An input/output buffer region is arranged around the plurality of sub chips. Each sub chip includes a sub chip control circuit region and a plurality of memory cell array blocks. Each memory cell array block includes a memory cell array region, a row decoder and control circuit region, a sense amplifier region and an input/output latch region.
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