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Abstract

In an input queuing self-routing switching system, each input buffer generates a reserve bit indicating that a cell of the buffer is a winner of a contention a previous contention cycle. A memory stores sets of path status bits and reads a corresponding set of path status bits for coupling to the input buffers as it receives cell destination addresses and reserve bits therefrom. Each path status bit indicates that a cell of the corresponding buffer is a contention loser if the reserve bit is not received during a subsequent contention cycle, or indicates that the cell is a winner of a contention when the reserve bit is received. Each input buffer is responsive to a contention timing signal for reading the destination address from a cell position identified by a cell pointer, and supplies the retrieved address and the reserve bit to the memory. The cell pointer of each buffer is shifted backwards when the corresponding path status bit indicates that the cell of the buffer is a contention loser and generates the reserve bit when the path status bit indicates that the cell is a contention winner. Each buffer further responds to a transmit timing signal for launching a cell therefrom to a self-routing network when that cell has been indicated as a contention winner by the path status bit.

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