Low power digital signal buffer circuit
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United States of America Patent
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Oct 25, 1994
Grant Date -
N/A
app pub date -
Jan 25, 1993
filing date -
Jan 25, 1993
priority date (Note) -
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status (Latency Note)
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Abstract
A low power signal buffer circuit for TTL signals includes a voltage reference controlled complementary MOSFET ('C-MOSFET') amplifier and a C-MOSFET inverter. The voltage reference controlled C-MOSFET amplifier receives a fixed reference voltage and a TTL input signal and provides a reference bias voltage. The C-MOSFET inverter has a pull-up P-type MOSFET which receives and is biased by the reference bias voltage, and a pull-down N-type MOSFET which receives the TTL input signal. The C-MOSFET inverter provides a TTL output signal with a substantially increased dynamic signal amplitude range. Current drain from the DC power supply for the buffer circuit decreases significantly as the TTL input signal state changes from 'low' to 'high' (e.g. logical 'zero' to logical 'one').
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