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Abstract

A bus interface for use in a processing system of the type including a processor such as a microprocessor or a microcontroller permits the processor to access either a non-multiplexed peripheral interface or a multiplexed peripheral interface, wherein the non-multiplexed peripheral interface includes an upper address input, a lower address input, and a data port, wherein the multiplexed peripheral interface includes a multiplexed address and data port, and wherein the processing device includes an internal upper address bus, an internal lower address bus, and an internal data bus. The bus interface includes an external upper address bus coupled to the upper address input, an external lower address bus coupled to the lower address input, and an external address/data bus coupled to the data port and to the multiplexed address and data port. The bus interface further includes bus interface circuit for coupling during an access to the non-multiplexed peripheral interface by the processor, the internal upper address bus to the external upper address bus, the internal lower address bus to the external lower address bus, and the internal data bus to the external address/data bus. During an access to the multiplexed peripheral interface by the processor, the bus interface circuit couples first the internal lower address bus to the external address/data bus and thereafter, the internal data bus to the external address/data bus.

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First Claim