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Abstract

A discrete cosine transformation processor includes first and second one-dimensional discrete cosine transformation circuits, a pre-processing circuit connected to the input of the one-dimensional discrete cosine processing circuit, and a post-processing circuit connected to the output of the one-dimensional discrete cosine processing circuit. The pre-processing circuit of the first one-dimensional discrete cosine processing circuit and the post-processing circuit of said second one-dimensional discrete cosine transformation circuit includes a shared first butterfly circuit, and the post-processing circuit of the first one-dimensional discrete cosine transformation circuit and the pre-processing circuit of the second one-dimensional discrete cosine transformation circuit includes a shared second butterfly circuit. A look-up table is used for two bits of each of two elements to a DCT matrix. The shared portion of the look-up tables can be extended for use with the forward and inverse DCT processing. A discrete cosine transformation processor includes a calculation block for sequentially performing a calculation for a predetermined bit position of each of a set of input signals, an adder/subtracter connected to the calculation block, a shift register for sequentially storing the established portion of an output signal of the adder/subtracter, and a resister for sequentially storing the carry portion used for the addition/subtraction at the next calculation cycle.

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