Importance

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Abstract

An error correction circuit is capable of performing correction errors in data at a high speed. A syndrome generator (2) calculates syndromes of RS codes based on partial data streams which are given from a data buffer (1). A received CRC generator (13) performs CRC coding on the partial data streams which are given from a data buffer (1) to thereby obtain received CRCs. An error pattern CRC generator (14) calculates error pattern CRCs of the respective partial data stream based on error patterns which are generated by an error pattern generation circuit (33). Under the control of a control circuit (40), the operations performed by the syndrome generator (2), the received CRC generator (13) and the error pattern CRC generator (14) are carried out at the same time. An improvement in the speed of error correction of the partial data streams performed by the error correction means directly leads to an improvement in the speed of the whole error correction.

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