Scheme for error handling in a computer system
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United States of America Patent
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-
Nov 1, 1994
Grant Date -
N/A
app pub date -
Apr 24, 1992
filing date -
Apr 24, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention is directed to a control flow logic device for handling data received from a bus by a bus interface, in response to a bus read transaction, and transferred to a processor. The control flow logic includes an error checker to check data received from the bus for hard errors and parity errors and an ECC generator to generate an ECC for the received data, the ECC being forced to a bad ECC when a hard error is detected by the error checker and to a good ECC in the absence of a hard error. An error signal generator is utilized to generate and transmit an error signal to the processor when there is a hard error or a parity error in the received data and a data mover transmits the received data and the ECC to the processor.
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