
US Patent No: 5,361,370
Number of patents in Portfolio can not be more than 2000
Single-instruction multiple-data processor having dual-ported local memory architecture for simultaneous data transmission on local memory ports and global port
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Nov 1, 1994
Issued date -
Oct 24, 1991
filing date -
07/782,332
serial no -
In Force
status
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Abstract
A single-instruction multiple-data video signal processor employs a dual-ported local memory architecture in each local memory including a dedicated port for transfers between the local memory and a global memory. A block transfer controller, in combination with the dedicated port, permit each access to the global memory by a datapath processor to be overlapped with its instruction processing, thus usually avoiding stalling of the video signal processor.
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First Claim
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International Classification(s)
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Cited Art
| Patent Info | (Count) | # Cites | Year |
|---|---|---|---|
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| 4,363,091 Extended address, single and multiple bit microprocessor | 28 | 1978 | |
| 4,338,675 Numeric data processor | 114 | 1980 | |
| 4,442,484 Microprocessor memory management and protection mechanism | 169 | 1980 | |
| 4,449,184 Extended address, single and multiple bit microprocessor | 44 | 1981 | |
| 4,783,757 Three input binary adder | 15 | 1985 | |
| 4,737,926 Optimally partitioned regenerative carry lookahead adder | 27 | 1986 | |
| 4,901,270 Four-to-two adder cell for parallel multiplication | 32 | 1988 | |
| 4,928,259 Sticky bit predictor for floating-point multiplication | 25 | 1988 | |
| 4,860,195 Microprocessor breakpoint apparatus | 27 | 1988 | |
| 4,926,387 Memory timing circuit employing scaled-down models of bit lines using reduced number of memory cells | 20 | 1988 | |
|
|
|||
| 4,816,993 Parallel processing computer including interconnected operation units | 38 | 1985 | |
| 4,979,096 Multiprocessor system | 30 | 1987 | |
| 5,010,477 Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations | 85 | 1987 | |
| 5,129,093 Method and apparatus for executing an operation request signal in a loosely coupled parallel computer having processor elements capable of updating memory contents and minimizing exclusive control of sharable distributed memories | 29 | 1988 | |
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| 4,891,787 Parallel processing system with processor array having SIMD/MIMD instruction processing | 102 | 1986 | |
| 5,038,282 Synchronous processor with simultaneous instruction processing and data transfer | 90 | 1988 | |
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| 4,570,220 High speed parallel bus and data transfer method | 137 | 1983 | |
| 4,807,109 High speed synchronous/asynchronous local bus and data transfer method | 49 | 1987 | |
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|
|||
| 4,907,148 Cellular array processor with individual cell-level data-dependent cell control and multiport input memory | 64 | 1988 | |
|
|
|||
| 5,113,523 High performance computer system | 142 | 1985 | |
|
|
|||
| 4,760,521 Arbitration system using centralized and decentralized arbitrators to access local memories in a multi-processor controlled machine tool | 33 | 1985 | |
|
|
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| 4,435,758 Method for conditional branch execution in SIMD vector processors | 97 | 1982 | |
|
|
|||
| 5,095,527 Array processor | 16 | 1991 | |
|
|
|||
| 4,837,682 Bus arbitration system and method | 98 | 1987 | |
|
|
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| 4,481,580 Distributed data transfer control for parallel processor architectures | 42 | 1983 | |
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| 4,396,906 Method and apparatus for digital Huffman encoding | 71 | 1980 | |
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|
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| 4,823,201 Processor for expanding a compressed video signal | 93 | 1987 | |
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| 4,922,418 Method for controlling propogation of data and transform through memory-linked wavefront array processor | 89 | 1988 | |
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| 4,792,894 Arithmetic computation modifier based upon data dependent operations for SIMD architectures | 13 | 1987 | |
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| 5,045,995 Selective operation of processing elements in a single instruction multiple data stream (SIMD) computer system | 63 | 1990 | |