Method of making a thin film transistor structure with improved source/drain contacts

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United States of America Patent

PATENT NO 5362660
SERIAL NO

07977967

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Abstract

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Minimum line spacing is reduced and line spacing uniformity is increased in thin film transistors by employing source/drain metallization having a first relatively thin layer of a first conductor and a second relatively thick layer of a second conductor. The second conductor is selected to be one which may be preferentially etched in the presence of the first conductor whereby the first conductor acts as an etch stop for the etchant used to pattern the second conductor portion of the source/drain metallization. This etching is preferably done using dry etching. Dry etching typically provides substantially better control of line width than wet etching. The etching of the second conductor can be done with a dry etch process which etches the photoresist at substantially the same rate as the second conductor whereby the second conductor is provided with a sidewall slope of substantially 45.degree. which improves the quality of passivation provided by subsequent deposition of a conformal passivating layer.

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Patent Owner(s)

Patent OwnerAddress
GENERAL ELECTRIC COMPANYSCHENECTADY NY 12345

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Holden, David E Grenoble, FR 3 119
Kwasnick, Robert F Schenectady, NY 66 1858
Possin, George E Schenectady, NY 47 1334
Saia, Richard J Schenectady, NY 28 1290

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