Importance

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Abstract

An information processor with a delayed interrupt device, comprises: a status register for storing information indicating whether or not a delayed interrupt process is processible; an execution unit for executing a normal instruction, a delayed interrupt request instruction, and a delayed interrupt process according to a delayed interrupt request that is based on the delayed interrupt request instruction; and an interrupt request unit for storing the delayed interrupt request transferred from the execution unit and sending the same to the execution unit. The interrupt request unit comprises a delayed interrupt request storage unit involving a plurality of storage portions for storing a plurality of delayed interrupt requests; a pointer for pointing one of the storage portions such that each delayed interrupt request is stored in the order of occurrence; and a selector for selecting one of the storage portions that is storing the oldest one of the delayed interrupt requests stored in the storage portions. Upon receiving an interrupt request from the interrupt request unit, the execution unit executes, according to the contents of the status register, a delayed interrupt process corresponding to the interrupt request.

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First Claim