Independent array grounds for flash EEPROM array with paged erase architechture
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United States of America Patent
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-
Nov 15, 1994
Grant Date -
N/A
app pub date -
Aug 23, 1993
filing date -
Aug 23, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An improved architecture for an array of flash EEPROM cells with paged erase is provided. The array is formed of a plurality of half-sectors. In each sector, the sources of the memory cell transistors are connected to a separate individual ground line. A ground line circuit is provided for generating a half-sector ground line signal. The separate individual ground line is connected to the ground line circuit for receiving the half-sector ground line signal which is at a predetermined positive potential during erase.
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