Method for constructing a dual sided, wire bonded integrated circuit chip package

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United States of America Patent

PATENT NO 5366933
SERIAL NO

08135732

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Abstract

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A method for constructing a dual sided integrated circuit chip package. A leadframe is formed comprising a set of die pads, and a set of lead fingers corresponding to each die pad. An integrated circuit die is disposed onto a first side and a second side of each die pad. Each integrated circuit die is wire bonded to the corresponding lead fingers. The temperature during the second side die attach and wire bonding steps is controlled and/or compatible materials are selected to prevent warping of the leadframe, and special steps are also implemented to eliminate mold flash, plastic mold cracking and overcuring and increasing the adhesion.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Foehringer, Richard Fair Oaks, CA 3 178
Golwalkar, Suresh V Folsom, CA 7 208
Kawashima, Shigeo Kitakyusyu, JP 3 178
Takatsuki, Ryo Ibaraki, JP 5 180
Wentling, Michael Cameron Park, CA 3 178

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