Importance

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Abstract

A programmable controller includes an interface circuit for communicating with a host CPU. The interface circuit includes a FIFO memory having a plurality of locations, each location receiving address and data information. The data information can either be an operand or a command. Whether the data information is an operand or a command is determined by one of the bits of the address. If the data information is an operand, it is stored at a location determined by the address. Accordingly, in a single host CPU cycle, the host CPU can write one word to the controller which comprises either a command or data and the address where the data can be stored. Multiple cycles are not required to provide a single instruction or data to the controller. Further, because a FIFO memory is used, a plurality of instructions are loaded into the controller and the controller and the host CPU can operate asynchronously. The controller also includes an EPROM for providing instructions to an internal CPU and a sequencer for providing addresses to the EPROM. The EPROM provides an output word including a bit field containing instructions for the sequencer, a bit field containing instructions for the CPU, and a bit field including instructions which are sent directly to the peripheral device. Accordingly, the controller can perform a plurality of instructions in parallel.

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First Claim