Method and apparatus for optimizing cost-based heuristic instruction scheduling
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United States of America Patent
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Nov 22, 1994
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app pub date -
Jul 7, 1993
filing date -
Mar 11, 1991
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Abstract
A method and apparatus for optimizing cost-based heuristic instruction scheduling for a pipelined processor is disclosed which has particular application to compile time instruction scheduling after code generation. Instruction scheduling is optimized by determining the optimal weights to be used by an apparatus for cost based heuristic instruction scheduling for a particular pipelined processor. The optimal weights are determined based on the lowest of the lowest costs incurred by different collections of interrelated weight sets. Each collection of interrelated weight sets comprises a randomly generated initial weight set and subsequent interrelated weight sets generated in a predetermined manner. The predetermined manner for generating subsequent weight sets facilitates rapid identification of the optimal weight set for a collection, and thereby rapid identification of the overall optimal weight set for the collections.
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