Importance

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Abstract

In order to obtain precise submodel control in a central processing unit, there is provided a subcounter which is controlled to count up from a beginning count as an instruction is executed and to count back down at the same rate to the reference count to obtain an effective delay before processing of the next instruction to be processed during normal program execution is started. Instruction transfer and decoding of the new instruction entering the pipeline is inhibited until the subcounter's most significant bit ('sign bit') changes state. If the subcounter is allowed to count during the entire count up and count down periods, a derated mode of 1/2 is achieved. To obtain other fractions, the subcounter is controlled to count periodically during one count direction period and to count full time during the other count direction period. In the exemplary embodiment, 1/4 and 3/4 derating is selectively achieved by the use of a modulo 3 counter which allows the subcounter to count only 1/3 the time in one or the other of the subcounter count up or count down periods.

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First Claim