Semiconductor memory device reading/writing data of multiple bits internally
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United States of America Patent
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Nov 29, 1994
Grant Date -
N/A
app pub date -
Oct 22, 1991
filing date -
Oct 24, 1990
priority date (Note) -
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Abstract
A semiconductor memory device includes a memory cell array divided into a plurality of block. In one region on the memory chip, four blocks, two input/output circuits, and two data buses are arranged. In the other region on the chip, four blocks, two input/output circuits, and two data buses are arranged. Each block in each region is divided into two sub-blocks corresponding to the two input/output circuits. Each data bus is connected between the corresponding input/output circuit in the same region and the corresponding two sub-blocks.
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