Importance

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Abstract

A digital clock circuit generates a high-speed clock and window pulses substantially centered about transitions of the high-speed clock in one quadrant of an integrated circuit (IC) and routes the high-speed clock and window pulses to other quadrants of the IC where a low-speed clock generator develops a low-speed clock signal from the window pulses. A control circuit checks alignment between the high-speed and low-speed clock signals and adjusts first and second shift registers to control the delay in generating the low-speed clock as necessary to maintain alignment. The first shift register controls the falling edge of the low-speed clock signal and the second shift register controls the rising edge of the low-speed clock signal.

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First Claim