Importance

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Abstract

The invention is a system and method for providing a breakpoint exception at any predetermined instruction address in a processor system of the type including an integrated circuit microprocessor and an instruction cache and memory management unit (CMMU) where code addresses are sent to the instruction CMMU and the instruction CMMU returns with code instructions and returns with a FAULT code reply signal when there is no reply code, and wherein an exception is forced in the microprocessor in response to the FAULT code reply signal. The system comprises at least one breakpoint register for storing a predetermined breakpoint address, a means for comparing the code addresses which are sent to the CMMU with the predetermined breakpoint address in the breakpoint register and for generating a match signal when equivalent addresses are detected, and a means coupled to the CMMU and responsive to said match signal for causing said CMMU to issue a FAULT code reply signal, whereby an exception is forced in the microprocessor. The system is especially suitable for use with the Motorola MC88100 processor and MC88200 CMMU.

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First Claim