Multi-processor having control over synchronization of processors in mind mode and method of operation
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United States of America Patent
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Dec 6, 1994
Issued Date -
N/A
app pub date -
May 17, 1993
filing date -
Nov 17, 1989
priority date (Note) -
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Abstract
There is disclosed a multiprocessor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip. Each processor can operate to execute the same instruction at the same time (SIMD mode) or different instructions at the same time (MIMD mode).
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