Three-dimensional ferroelectric integrated circuit without insulation layer between memory layers
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United States of America Patent
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Sep 21, 1993
Grant Date -
N/A
app pub date -
Sep 30, 1992
filing date -
Sep 30, 1992
priority date (Note) -
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Abstract
A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.
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