Compact adapter package providing peripheral to area translation for an integrated circuit chip
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United States of America Patent
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Jan 3, 1995
Issued Date -
N/A
app pub date -
Jun 9, 1994
filing date -
Feb 26, 1991
priority date (Note) -
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status (Latency Note)
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Abstract
An peripheral to area adapter for an integrated circuit chip. The adapter comprises pads on an upper surface of a support in a pattern corresponding to the terminals on a integrated circuit, planar reroute lines on the upper surface with first ends at the pads, and vertical conductive vias extending through the support. The vias are connected at the upper surface to the second ends of the reroute lines. The vias are connected at the lower surface of the support to an area array of coupling elements. The pads and reroute lines can be fabricated on a tape-automated-bonding (TAB) frame support and personalized to match a particular configuration of terminals or bumps on a chip. The coupling elements can form a generic array compatible with a wide variety of interconnect substrates.
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