Three dimensional famos memory devices and methods of fabricating
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United States of America Patent
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Jan 3, 1995
Grant Date -
N/A
app pub date -
Dec 14, 1992
filing date -
Dec 14, 1992
priority date (Note) -
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Abstract
Memory cell transistors are provided in which pillar structures or column structures (12, 12a, 14, and 14a) are formed at the face of a semiconductor substrate (10). Floating gates (46) and control gates (52) are formed adjacent to the pillar structures or column structures (12, 12a, 14, and 14a). The floating gates (46) and control gates (52) are insulatively disposed by gate oxide layer (42) and insulating layer (50). Source regions (36, 40, and 48) are implanted in the semiconductor substrate (10). Drain regions (38) are also implanted in the pillar structures or column structures (12, 12a, 14 and 14a).
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