Cache memory system for vector processing
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United States of America Patent
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Jan 3, 1995
Grant Date -
N/A
app pub date -
May 14, 1992
filing date -
May 14, 1992
priority date (Note) -
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Abstract
A cache memory system for use during vector processing in a processor. The processor contains a central processing unit (CPU) and a main memory. The system includes a vector cache memory, a first address register, a main memory address calculation unit, and a cache address calculation unit. The first register stores a first address associated with an instruction executed by the CPU. The main memory address calculation unit is coupled to the first address register for calculating a second address utilizing the first address and vector stride data associated with said executed instruction. The second address is utilized to access the main memory. The cache address calculation unit is coupled to both the first address register and the main memory address calculation unit for calculating the third address utilizing portions of the first address and portions of the second address. The third address is utilized to access the vector cache memory.
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