Parallel processor with array of clustered processing elements having inputs seperate from outputs and outputs limited to a maximum of two per dimension
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United States of America Patent
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Jan 3, 1995
Grant Date -
N/A
app pub date -
Dec 17, 1991
filing date -
Dec 20, 1990
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A processor is provided (FIG. 1) comprising a plurality of processing elements (10) arranged into D dimensions and divided into clusters (11), wherein all elements in a cluster have a bus (13) for communicating therebetween. Each element is a member of one cluster in each dimension. Each element in a cluster is connected to the bus in that cluster by output means (FIG. 3), for sending messages to a plurality of other elements in the cluster, and separate input means corresponding to each other element in the cluster for receiving messages from each other element on the corresponding separate input means.
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