FPGA having PFU with programmable output driver inputs
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jan 10, 1995
Grant Date -
N/A
app pub date -
May 21, 1993
filing date -
May 21, 1993
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
In accordance with the present invention, a field programmable gate array includes at least one programmable function unit. The programmable function unit has first and second logic circuits, each providing an output, and first and second output drivers, each having an input. The input of each output driver is adapted to be selectively coupled to the output of either of the logic circuits. A programmable interconnection is provided to selectively couple the input of the two output drivers to the output of a selective one of the logic circuits.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully